培训方式以讲课和实验穿插进行。
Cadence? Incisive? Enterprise Simulato主要利用系统级至门级的涵蓋率來驱动功能验证和除错分析进一步促进的验证的效率及可预测性。Cadence Incisive Enterprise Simulator?提供testbench制作、共用和分析能力，可从系统级至RTL再到门级验证其设计，利用此环境从计划至完成皆可支援涵蓋范围驱动的运算法，而其原位编译的模组可在传统同步模拟加速並同时模拟关于behavior、transation(TLM)?、RTL和门级模型，以达到有效改善同步模拟的不良性能。它也支援工业标准的验证语言並且与开放验证运算法相容(OVM)，因此工程师能迅速简单地整合Cadence Incisive Enterprise Simulator以建立所需要的验证流程。
COURSE OUTLINE
MDV (Metric Driven Verification) foundations workshop
·?????????MDV Foundations introduction
–??MDV Foundations Planning
–??Introduction to Planning
·?????????Verification Plan Development
–??Lab 1: Launching Your First Regression
–??Lab 2: Review the Default vPlan View in Enterprise Manager
–??Lab 3: Creating Reusable Verification Plans
–??Lab 4: Creating a Top Level Verification Plan
–??Lab 5: Detecting Changes in the New Specification
–??Lab 6: Review the vPlan in vManager
·?????????MDV Foundations Infrastructure ?
–??Lab 1: Your First Enterprise Manager Regression
–??Lab 2: Integrating project build and run
·?????????MDV Foundations Management
–??Lab 1: Create your own first failures view
–??Lab 2: Rerun Failures
–??Lab 3: vPlan Analysis
–??Lab 4 : Report generation
?
Low Power Verification Workshop
???????????Introduction
–????????Introduction to Low Power Terminology
–????????CPF Creation
–????????Lab: Understanding the power information from a CPF file - Solution
???????????Low Power Simulation Verification
–????????Verification Planning and Metrics for Low Power
–????????Low-Power Simulation
–????????TCL Commands for Debug
–????????Debugging with SimVision
–????????Automatic Assertions
–????????Lab: Low-Power Simulation Debug
Assura Verification
The Assura? Verification course covers aspects of using the Assura DRC and Assura LVS tools for design rule checks, short location, and layout-versus-schematic checks. In labs, the student executes DRC and LVS and debugs error results.
Learning Objectives
In this course you will:
?
o Verify your physical IC design with Assura Verification?
?
o Set up and run DRC and LVS?
?
o?Locate and display results from DRC and LVS runs?
?
o Run verification in various input and run modes
Audience
?
o CAD Developers
?
o Design Engineers
?
o? Layout Designers
Prerequisites
?
o Layout design experience
?
o Physical verification experience
?
o UNIX OS
Course Agenda
Unit 1
?
o?Introduction?
?
o?Using Assura Verification?
?
o?Operational details?
?
o?Inputs and outputs?
?
o?Interactive debugging environment?
?
o?DRC and LVS runs
?
o?Running design-rule checks (DRC)?
?
o?DRC error debugging techniques?
?
o?Error Layer Window?
?
o?Setting up DRC run parameters
Unit 2
?
o?Running design rule checks (continued)?
?
o?Antenna check?
?
o?Density check
?
o?Running layout versus schematic (LVS) checks?
?
o?Understanding and debugging LVS check reports?
?
o?Setting up LVS run parameters?
?
o?Displaying errors using the graphical user interface?
?
o Locating LVS errors
Unit 3
?
o Running layout versus schematic checks (continued)?
?
o?Debugging LVS with multiple errors?
?
o?Using the main debugging tools?
?
o?Mismatched nets and mismatched devices?
?
o?Shorts locator and opens locator?
?
o?Malformed devices?
?
o?Pins, parameters, and rewire tools
?
o?Unguided debugger lab module?
?
o?Running an electrical rules check (ERC)
|
