曙海教育集团
上海:021-51875830 北京:010-51292078
西安:029-86699670 南京:4008699035
成都:4008699035 武汉:027-50767718
广州:4008699035 深圳:4008699035
沈阳:024-31298103 石家庄:4008699035☆
全国统一报名免费电话:4008699035 微信:shuhaipeixun或15921673576 QQ:1299983702
首页 课程表 报名 在线聊 讲师 品牌 QQ聊 活动 就业
嵌入式OS--4G手机操作系统
嵌入式硬件设计
Altium Designer Layout高速硬件设计
开发语言/数据库/软硬件测试
芯片设计/大规模集成电路VLSI
其他类
 
     Design Compiler高级培训班(Synopsys)
   班级规模及环境--热线:4008699035 手机:15921673576( 微信同号)
       坚持小班授课,为保证培训效果,增加互动环节,每期人数限3到5人。
   上课时间和地点
上课地点:【上海】:同济大学(沪西)/新城金郡商务楼(11号线白银路站) 【深圳分部】:电影大厦(地铁一号线大剧院站)/深圳大学成教院 【北京分部】:北京中山学院/福鑫大楼 【南京分部】:金港大厦(和燕路) 【武汉分部】:佳源大厦(高新二路) 【成都分部】:领馆区1号(中和大道) 【沈阳分部】:沈阳理工大学/六宅臻品 【郑州分部】:郑州大学/锦华大厦 【石家庄分部】:河北科技大学/瑞景大厦 【广州分部】:广粮大厦 【西安分部】:协同大厦
最近开课时间(周末班/连续班/晚班)
Design Compiler高级培训班:v2020年10月1日(请抓紧报名)
   实验设备
     ☆资深工程师授课

        
        ☆注重质量
        ☆边讲边练

        ☆合格学员免费推荐工作

        ☆合格学员免费颁发相关工程师等资格证书,提升您的职业资质

        专注高端培训15年,曙海提供的证书得到本行业的广泛认可,学员的能力
        得到大家的认同,受到用人单位的广泛赞誉。

        ★实验设备请点击这儿查看★
   最新优惠
       ◆在读学生凭学生证,可优惠500元。
   质量保障

        1、培训过程中,如有部分内容理解不透或消化不好,可免费在以后培训班中重听;
        2、课程完成后,授课老师留给学员手机和Email,保障培训效果,免费提供半年的技术支持。
        3、培训合格学员可享受免费推荐就业机会。

  Design Compiler高级培训班(Synopsys)
  课程描述

       DC是把HDL描述的电路综合为跟工艺相关的、门级电路。并且根据用户的设计要求,在时序和面积,时序和功耗上取得最佳的效果。在floor planning和placement和插入时钟树后 返回DC进行时序验证。其最高版本被称为DC Ultra。在Synopsys软件中完整的综合方案的核心是DC UltraTM,对所有设计而言它也是最好级别的综合平台。DC Ultra添加了全面的 数据通路和时序优化技术,并通过工业界的反复证明。

   课程内容

 第一阶段

       综合的定义;ASIC design flow;Synopsys Design Compiler的介绍;Tcl/Tk 功能介绍;Synopsys technology library;Logic synthesis的过程;Synthesis 和layout的接口——LTL;Post_layout optimization;SDF文件的生成;其他高级综合技巧与总结。

  Overview?
  
   This course covers the ASIC synthesis flow using Design Compiler -- from reading in an RTL design (Verilog and VHDL) to generating a final gate-level netlist. You will learn how to read in your design file(s), specify your libraries, constrain a complex design for area and timing, partition your design? hierarchy for synthesis, apply synthesis techniques to achieve area and timing closure, analyze the synthesis results, and generate output data that works with downstream layout tools. You will verify the logic equivalence of synthesis transformations (such as Datapath optimizations and Register Retiming) to that of an RTL design using Formality. The course includes labs to reinforce and practice key topics discussed in lecture. All the covered commands and flows are printed separately in a 4-page Job Aid which the student can refer to back at work.
  
   Objectives?
  
   At the end of this workshop the student should be able to:?
   ◆Create a setup file to specify the libraries that will be used?
   ◆Read in a hierarchical design?
   ◆Partition a design's hierarchy optimally for synthesis?
   ◆Constrain a complex design for area and timing, taking into account different environmental attributes such as output loading, input drive strength, process, voltage and temperature variations, as well as post-layout effects such as clock skew and net parasitics?
   ◆Select the appropriate compile flow for your project?
   ◆Execute the recommended synthesis techniques within each compile flow to achieve area and timing closure?
   ◆Perform test-ready synthesis when appropriate?
   ◆Verify the logic equivalence of a synthesized netlist to that of an RTL design?
   ◆Write DC-Tcl scripts to constrain and compile designs?
   ◆Generate and interpret timing, constraints and other debugging reports?
   ◆Understand the effect that RTL coding style can have on synthesis results?
   ◆Generate output data (netlist, timing/area constraints, physical constraints scan-def) that works with downstream physical design?or?layout tools?
  
   Audience Profile
  
   ASIC digital designers who are going to use Design Compiler to synthesize Verilog?or?VHDL RTL modules to generate gate-level netlists.
  
   Prerequisites
  
   To benefit the most from the material presented in this workshop, you should:
   ◆Understand the functionality of digital sequential and combinational logic?
   ◆Have familiarity with UNIX and a UNIX text editor of your choice?
   ◆No prior Design Compiler knowledge?or?experience is needed?
  
  第二阶段
  
   Unit 1
   ◆Introduction to Synthesis
   ◆Setting Up and Saving Designs
   ◆Design and Library Objects
   ◆Area and Timing Constraints
   ◆Setting Up and Saving Designs

  • Loading Technology and Design Data
  • Design and Library Objects
  • Timing Constraints



   Unit 2
   ◆Partitioning for Synthesis
   ◆Environmental Attributes
   ◆Compile Commands
   ◆Timing Analysis
   ◆More Constraint Considerations
  

  • Compiling RTL to Gates
  • Timing Analysis


Unit 3
◆More Constraint Considerations
◆Multi-Clock Designs
◆Synthesis techniques and Flows
◆Post-Synthesis Output Data
◆Conclusion
Congestion Analysis and Optimization

Unit 4

Unit 5

Clock Tree Synthesis

Multi Scenario Optimization

?

Unit 6

Design Planning

Routing and Crosstalk

Chip Finishing and DFM

Customer Suppor

第三阶段

第一部分
unit 1. Introduction to Synthesis
? Execute the basic steps of synthesis on a simple design
? Use two commands to modify the partitioning of a design
? Gain familiarity with SolvNet ,your essential resource for?
  solving your design compiler problems
unit 2. Setup, Libraries and Objects
unit 3. Partitioning for Synthesis
unit 4. DC Tcl - An Introduction

第二部分
unit 5. Timing and Area
?Constrain simple designs for area, timing and design
  rule constraints (DRC)
? Generate ,view and analyze timing and DRC reports
unit 6. Environmental Attributes
unit 7. Design Rules and Min Timing
unit 8.Timing Analysis

第三部分
unit 9.Multiple Clock/Cycle Designs
? Constrain and analyze multi-clock,
  asynchronous and multi-cycle path designs
? State several key steps that occur during a default compile?
? Enable Design Compiler to work harder in fixing design violations
? Describe some issues that surround synthesis and where to find additional information?

unit 10. Optimization

unit 11.Compile Strategies

unit 12. Before,During and After
 

   培养对象

        从事ASIC 设计与验证的工程师,希望更深入了解Design Compiler和芯片综合(chip synthesis)技术的工程师,希望从事ASIC设计工程师的理工科背景大四学生或硕士研究生。

   入学要求

        学员学习本课程应具备下列基础知识:
        ◆ 对数字集成电路设计有一定理解;
        ◆ 了解Verilog/VHDL 语言。