培训方式以讲课和实验穿插进行。
Assura Verification
The Assura? Verification course covers aspects of using the Assura DRC and Assura LVS tools for design rule checks, short location, and layout-versus-schematic checks. In labs, the student executes DRC and LVS and debugs error results.
Learning Objectives
In this course you will:
?
o Verify your physical IC design with Assura Verification?
?
o Set up and run DRC and LVS?
?
o?Locate and display results from DRC and LVS runs?
?
o Run verification in various input and run modes
Audience
?
o CAD Developers
?
o Design Engineers
?
o? Layout Designers
Prerequisites
?
o Layout design experience
?
o Physical verification experience
?
o UNIX OS
Course Agenda
Unit 1
?
o?Introduction?
?
o?Using Assura Verification?
?
o?Operational details?
?
o?Inputs and outputs?
?
o?Interactive debugging environment?
?
o?DRC and LVS runs
?
o?Running design-rule checks (DRC)?
?
o?DRC error debugging techniques?
?
o?Error Layer Window?
?
o?Setting up DRC run parameters
Unit 2
?
o?Running design rule checks (continued)?
?
o?Antenna check?
?
o?Density check
?
o?Running layout versus schematic (LVS) checks?
?
o?Understanding and debugging LVS check reports?
?
o?Setting up LVS run parameters?
?
o?Displaying errors using the graphical user interface?
?
o Locating LVS errors
Unit 3
?
o Running layout versus schematic checks (continued)?
?
o?Debugging LVS with multiple errors?
?
o?Using the main debugging tools?
?
o?Mismatched nets and mismatched devices?
?
o?Shorts locator and opens locator?
?
o?Malformed devices?
?
o?Pins, parameters, and rewire tools
?
o?Unguided debugger lab module?
?
o?Running an electrical rules check (ERC)
|
